Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-Vt Domain By Architectural Folding

This manuscript presents the digital hardware realization of a wavelet based event detector for cardiac pacemaker applications. The architecture of the detector is partially folded to minimize hardware cost. An energy model is applied to evaluate the energy efficiency in the sub-threshold (sub-VT ) domain. The design is synthesized in 65 nm low leakage-high threshold CMOS technology, and it is shown that folding reduces the area cost by 30.6 %. Due to folding, energy efficiency of the circuit is increased by 14.4 % in the sub-VT regime, where the circuit dissipates 3.3 pJ per sample at VDD=0.26 V.